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ispLSI 1048
(R)
In-System Programmable High Density PLD Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- 8000 PLD Gates -- 96 I/O Pins, Ten Dedicated Inputs -- 288 Registers -- High-Speed Global Interconnects -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Security Cell Prevents Unauthorized Copying * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 80 MHz Maximum Operating Frequency -- fmax = 50 MHz for Industrial Devices -- tpd = 15 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology -- 100% Tested * IN-SYSTEM PROGRAMMABLE -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging * COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0
Output Routing Pool
Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5
Output Routing Pool
DQ
A1 A2 A3 A4 A5 A6 A7
D6
Logic
DQ
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
DQ DQ
Global Routing Pool (GRP)
Array
GLB
D4 D3 D2 D1 D0 CLK
B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
Description
The ispLSI 1048 is a High-Density Programmable Logic Device which contain 288 Registers, 96 Universal I/O pins, ten Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1048 devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 (see figure 1). There are a total of 48 GLBs in the ispLSI 1048 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
1048_06
1
Specifications ispLSI 1048
Functional Block Diagram
Figure 1. ispLSI 1048 Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0
IN 7 IN 6 I/O 6 I/O 6 I/O 6 I/O 6 I/O 5 I/O 5 I/O 5
A1 A2 A3 A4 A5 A6 A7
D5 D4 D3 D2 D1 D0
Output Routing Pool (ORP)
lnput Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
Global Routing Pool (GRP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
D7 A0 D6 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool (ORP) Input Bus Output Routing Pool (ORP) Input Bus
Clock Distribution Network
I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 5 I/O 4 I/O 4
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
Megablock
ispEN
SDO/ IN3
I/O I/O I/O I/O 16 17 18 19
I/O I/O I/O I/O 20 21 22 23
I/O I/O I/O I/O 24 25 26 27
I/O I/O I/O I/O 28 29 30 31
IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35
I/O I/O I/O I/O 36 37 38 39
I/O I/O I/O I/O 40 41 42 43
I/O I/O I/O I/O 44 45 46 47
YYYY 0123
0139F(1)-48-isp
The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1048 device are selected using the Clock Distribution Network. Four dedicated clockpins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0 on the ispLSI 1048 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs (one dedicated input in Megablock B and E) and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The ispLSI 1048 device contains six of these Megablocks.
2
Specifications ispLSI 1048
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
MIN. 4.75 4.5 0 MAX. 5.25 5.5 0.8 Supply Voltage Commercial TA = 0C to +70C Industrial TA = -40C to +85C Input Low Voltage Input High Voltage 2.0 Vcc + 1
PARAMETER MAXIMUM1 8 UNITS pf Dedicated Input Capacitance I/O and Clock Capacitance 10 pf
PARAMETER MINIMUM 20 10000 MAXIMUM -- --
Max. Junction Temp. (TJ) with Power Applied ... 150C
UNITS V V V
VCC VIL VIH
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
TEST CONDITIONS
C1 C2
VCC=5.0V, VIN=2.0V
VCC=5.0V, VI/O, VY=2.0V
1. Guaranteed but not 100% tested.
Data Retention Specifications
UNITS Years
Table 2- 0008B
Data Retention
Erase/Reprogram Cycles
Cycles
3
Specifications ispLSI 1048
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see figure 2)
Test Condition A B R1
Active High Active Low
C
Active High to Z at VOH - 0.5V Active Low to Z at VOL + 0.5V
DC Electrical Characteristics
SYMBOL
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Table 2- 0003
3-state levels are measured 0.5V from steady-state active level.
R2
CL
*CL includes Test Fixture and Probe Capacitance.
470
390 390
35pF 35pF 35pF 5pF

470
390 390
470
390
5pF
Over Recommended Operating Conditions
CONDITION
PARAMETER
MIN. - - - - - - - -
TYP.3 - - - - - - -
MAX. 0.4 -
UNITS V V A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
ICC2,4
Output Low Voltage
IOL =8 mA
Output High Voltage
IOH =-4 mA
2.4
Input or I/O Low Leakage Current isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current
0V VIN VIL (MAX.) 3.5V VIN VCC 0V VIN VIL
-10 10
Input or I/O High Leakage Current
0V VIN VIL (MAX.)
-150 -150 -200 235 260
VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fTOGGLE = 1 MHz
Operating Power Supply Current
Commercial Industrial
165 165
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using twelve 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of this Lattice Semiconductor Data Book or CD-ROM to estimate maximum Table 2- 0007A-48-isp ICC.
4
Specifications ispLSI 1048
External Timing Parameters
Over Recommended Operating Conditions
-80
- - 80
1 tsu2 + tco1
52 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback ( Clock Frequency, Max Toggle4
-70
15 20 - - - - - - - - - - 71.4 41.7 83 9 - 0 - 0 - - - 6 6 2 18 23 - - - - - - - - - -
-50
24 30.7 - - - - 16 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
- - - - - - - 100 7 - 0 - 0 - - - 5 5 2 71.4 12 - 0 - 0 - - - 7 7 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock A 10 12 10 12 16 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 12 17 18 18 - - - - 14 17 20 20 - - - - A B - - - - 10 10 13 C 16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 2.7 8.7 6.5 6.5
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5
1. 2. 3. 4. 5.
A A A -
53.6 31.3
)
50
18.7 22.7 26.7 26.7 - - - -
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section.
Table 2- 0030A-48/80,70,50
5
Specifications ispLSI 1048
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-80
-70
-50
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
23 24 25 26 I/O Register Hold Time after Clock I/O Register Clock to Out Delay Dedicated Input Delay I/O Register Reset to Out Delay 0.9 - - - - - - 2.5 2.9 5.0 - - - 3.0 3.5 6.0 27 28 29 30 31 32 GRP Delay, 1 GLB Load - - - - - - 2.1 2.5 3.3 4.2 5.0 - - - - - - 2.5 3.0 4.0 5.0 6.0 - - - - - - GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 48 GLB Loads 13.3 16.0 33 34 35 36 37 38 39 40 41 42 43 44 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay XOR Adjacent Path Delay3 20 Product Term/XOR Path Delay - - - - - 5.4 6.5 7.6 8.4 0.8 - - - - - - - 6.5 7.0 7.5 9.5 1.0 - - - - - - - GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay 0.8 5.0 - - - - 1.5 6.0 - - - - 2.0 8.0 - - - - 2.1 2.1 8.3 8.8 6.3 2.5 2.5 9.0 7.5 GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Clock Delay 10.0 GLB Product Term Output Enable to I/O Cell Delay 2.9 3.5 4.6 45 46 ORP Delay - - 3.2 1.3 - - 3.5 1.5 - - ORP Bypass Delay
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp48
20 21 22
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock
- - 5.3 1.5
2.5 3.3 - -
- - 6.0 0.5
3.0 4.0 - -
- - 8.1
4.0 5.3 - - 3.9 4.6 8.0
ns ns ns ns ns ns ns
3.3 4.0 5.3 6.7 8.0 21.3
ns ns ns ns ns ns
GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp
8.6 9.3 10.0 12.7 1.3 - - 3.3 3.3 13.3 11.9 9.9
ns ns ns ns ns ns ns ns ns ns ns ns
4.7 2.0
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2- 0036A-48/80,70,50.eps
6
Specifications ispLSI 1048
Internal Timing Parameters1
-80 -70 -50
PARAMETER
#
2
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
- - -
2.5 4.2 4.2
- - -
3.0 5.0 5.0
- - -
4.0 6.7 6.7
ns ns ns
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
50 51 52 53 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line 4.2 3.3 0.8 3.3 0.8 4.2 5.0 4.2 5.0 4.2 5.0 4.0 1.0 4.0 1.0 5.0 6.0 5.0 6.0 5.0 6.7 5.3 1.3 5.3 1.3 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers - 9.2 - 8.0 -
6.7 8.0 6.6 8.0 6.6
ns ns ns ns ns
Global Reset tgr 55
10.6
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
7
Specifications ispLSI 1048
ispLSI 1048 Timing Model
I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
#26 I/O Reg Bypass #20 Input D Register Q RST #21 - 25 GRP 4 #28 GRP Loading Delay #27, 29, 30, 31, 32 4 PT Bypass #33 20 PT XOR Delays #34, 35, 36 #55 D RST GLB Reg Bypass #37 GLB Reg Delay Q #38, 39, 40, 41 ORP Bypass #46 ORP Delay #45 #47 I/O Pin (Output) #48, 49
I/O Pin (Input)
#55 Reset
Y1,2,3
Y0
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 5.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (3.0 + 3.0 + 3.5) = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 6.0 ns = (3.0 + 3.0 + 7.5) + (6.0) - (3.0 + 3.0 + 7.5)
th
tco
= Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 22.5 ns = (3.0 + 3.0 +7.5) + (2.5) + (3.5 + 3.0)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 6.5 ns = (3.0 + 3.0 + 7.5) + (1.5) - (5.0 + 2.5 + 1.0) = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 5.0 ns = (5.0 + 2.5 + 5.0) + (6.0) - (3.0 + 3.0 + 7.5)
th
tco
= Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 21.5 ns = (5.0 + 2.5 + 5.0) + (2.5) + (3.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1048-70.
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
Clock Distribution #51, 52, 53, 54 #50 Control RE PTs OE #42, 43, CK 44
8
Specifications ispLSI 1048
Maximum GRP Delay vs GLB Loads
8 7 6
GRP Delay (ns)
ispLSI 1048-50
ispLSI 1048-70 ispLSI 1048-80
5 4 3 2 1 0
Power Consumption
Power consumption in the ispLSI 1048 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
250 200 150 100
ICC can be estimated for the ispLSI 1048 using the following equation: ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A-48-80-isp
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
4 8 GLB Loads 12 16
0126A-48-80-isp
ure 3 shows the relationship between power and operating speed.
ispLSI 1048
ICC (mA)
50
0
10
20
30
40
50
60
70
80
fmax (MHz)
Notes: Configuration of Twelve 16-bit Counters Typical Current at 5V, 25C
9
Specifications ispLSI 1048
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 IN 4 IN 6 - IN 11 ispEN
PQFP PIN NUMBERS
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103, 109,110,111,112,113,114, 115,116,117,118,119,120, 1, 2, 3, 4 5, 6, 7, 8, 9, 10, 11, 12 48, 79,104,105, - 108, 13 17
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
SDI/IN 01
MODE/IN 11
SDO/IN 31
SCLK/IN 51
RESET Y0 Y1
Y2
Y3
GND
VCC
1. Pins have dual function capability.
Table 2- 0002C-48-isp
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
19 44 47 73 18 14 78 75 74 46, 76,106, 16 15, 45, 77, 107 Ground (GND) VCC
Dedicated input pins to the device. (IN 2 and IN 9 not available)
Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.
10
Specifications ispLSI 1048
Pin Configuration
ispLSI 1048 120-Pin PQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
ispLSI 1048
Top View
1. Pins have dual function capability.
I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1MODE/IN 1 VCC GND 1SDO/IN 3 IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
0124 -48-isp
I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND 1ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 IN 5/SCLK1 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36
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Specifications ispLSI 1048
Part Number Description
ispLSI 1048 -- XX
Device Family
X
X
X
Grade Blank = Commercial I = Industrial Package Q = PQFP Power L = Low
Device Number Speed 80 = 80 MHz fmax 70 = 70 MHz fmax 50 = 50 MHz fmax
ispLSI 1048 Ordering Information
U C SE O is Mp ML ER SI C 10 IA 4 D L 8E ES & A IG IN F N D OR SU ST N R EW IA L
COMMERCIAL Family
0212-80B-isp1048
fmax (MHz) tpd (ns)
80 15 70 50
Ordering Number ispLSI 1048-80LQ
Package
120-Pin PQFP
ispLSI
18 24
ispLSI 1048-70LQ
120-Pin PQFP
ispLSI 1048-50LQ
120-Pin PQFP
INDUSTRIAL
Family ispLSI
fmax (MHz) tpd (ns)
50 24
Ordering Number
Package
ispLSI 1048-50LQI
120-Pin PQFP
Table 2- 0041A-48-isp
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